1. Field of the Invention
The present invention relates to memory cells and methods for manufacture thereof, and more specifically, to a method for manufacturing a floating gate with improved tunnel oxide reliability.
2. Discussion of the Related Art
Nonvolatile memory devices such as electrically programmable read-only memory (EPROM) and electrically-erasable programmable read-only memory (EEPROMs) are extensively used. An EPROM or EEPROM integrating circuit has a large number of memory cells each having an electrically isolated gate, referred to as a floating gate. Data is stored in the memory cells in the form of charge on the floating gates. Charge is transported to or removed from the floating gates by program and erase operations, respectively.
Another type of non-volatile memory is flash memory which is a derivative of EPROM and EEPROM. However, flash memory has a distinct advantage over EPROM in that certain types of flash memory can be erased and reprogrammed inside a system, with no special voltages needed. Flash memory devices are also lower in cost and available in higher densities than EEPROM. As a result, flash memory is well-suited to a number of end-product applications, including existing embedded-system flash applications as personal computers and peripherals, telecommunication switches, cellular phones, and internetworking, instrumentation and automotive devices, and emerging consumer-oriented voice, image and data storage products such as digital still cameras, digital voice recorders, and personal digital assistants (PDAs).
Flash memory can be erased and reprogrammed in units of memory called blocks. The erasure is caused by Fowler-Nordheim tunneling in which electrons pierce through a thin dielectric material to remove an electronic charge from a floating gate associated with each memory cell.
FIG. 1 shows a cross-sectional view of a portion of the memory cell in a typical NAND-type flash memory. Memory cell 10 typically includes a source region 16, a drain region 18 and a channel region 14 in a substrate 12, and a stacked gate structure 20 overlying the channel region 14 and separated by a dielectric layer 22. Source region 16 and drain region 18 are constructed from an N+ type of high impurity concentration and are separated by a predetermined space of a channel region 14 which is of P-type. Substrate 12 is an N-type substrate.
Stacked gate structure 20 typically includes a floating gate 24 formed by a first polysilicon (poly I) layer and a control gate 28 formed by a second polysilicon (poly II) layer. Floating gate 24 is isolated from control gate 28 by an interpoly dielectric layer 26 and from channel region 14 by a thin oxide layer 22 which is approximately 100 .ANG. (angstroms) thick. The thin oxide layer 22 is commonly referred to as the tunnel oxide. Interpoly dielectric layer 26 is often a multilayer insulator such as an oxide-nitride-oxide (ONO) stack.
Because polysilicon has interleaving large and small grain structures, polysilicon has many grain boundaries, thereby causing rough surface interface between floating gate 24 and tunnel oxide 22 and between floating gate 24 and interpoly dielectric layer 26. The rough surface interface causes defects. Amorphous silicon (.alpha.-Si), on the other hand, has very few grain boundaries, thus producing very smooth intersurfaces and therefore, lower resistivity.
The channel region 14 of memory cell 10 conducts current between source region 16 and drain region 18 in accordance with an electric field developed in channel region 14 by stacked gate structure 20. Because floating gate 24 is highly doped (e.g., approximately 1.times.10.sup.20 atom/cm.sup.3). The doping level of floating gate 24 is limited by charge retention. If the doping level is too high, dopant segregation to tunnel oxide 22 increases, causing tunnel oxide integrity problems such as impurity contamination and high defect density. Higher doping levels also produce higher surface roughness between floating gate 24 and tunnel oxide layer 22 and between floating gate 24 an interpoly dielectric layer 26. The rough surface causes high interface resistance and lower the oxide dielectric strength of interpoly dielectric layer 26, thereby decreases circuit performance, causes reliability problem and program/erase endurance cycling charge gain (loss) problem.
Floating gate 24 that is lightly doped or not doped can eliminate some of the above-described problems. However, lower doping levels degrade circuit performance because of poly I depletion of floating gate 24. Further, floating gate 24 and the select gate (not shown) are typically made from the same layer of material. Thus, lowering or eliminating the doping would undesirably lower the conductivity of the select gates.
Therefore, what is needed is a floating gate structure that has good charge retention as well as good interface properties.